English to French Tech/Engineering Patents (in a patent) Module for monitoring industrial processes

For each analog datum of the signal R, sampled by the module 62 at 664585 Hz, as represented in the diagram of Figure 5, which represents the serial signal 10 T generated by the multiplexer 63 and a clock signal CK that times operation thereof, the multiplexer 63 receives a start bit SB with a duration of 4 high bits (4 high clock cycles).

Then, the multiplexer 63 enters the first bit C0, in a clock cycle, followed by a logic zero in the next clock cycle, then the second bit Cl, and again a zero, each entry having the duration of one clock cycle, until the final bit C23 is entered, followed, at the next clock cycle, by a final zero. Entry of the zeros in the multiplexer 63 is symbolized by an appropriate input 0 in Figure 4.